1. Field of the Invention
The present invention relates generally to standby power systems for semiconductor chips such as dynamic random access memory (DRAM), and, particularly, to an on-chip, self-refresh voltage generator system and method for reducing the power of on-chip voltage generators during non-active mode periods.
2. Discussion of the Prior Art
Normally, all the on-chip voltage generators must be maintained active even during the standby, or sleep mode in order to keep voltage levels for certain operations during these modes. Additionally, when the chip resumes normal operation, all the voltage levels must be ready immediately for normal operations. For these reasons, the on-chip voltage generators are designed to have both active generators and standby generators with the active generators being used during the active mode, and the standby generators being kept on constantly after power-on to guard the voltage drop due to charge leakage due to any mechanism. In semiconductor chips, there are many disadvantages of implementing a standby generator. For example: 1) the standby generators require extra chip areas; 2) the standby generator consumes DC power, e.g., a body back bias voltage (Vbb) standby pump consumes 15 uA; and 3) during the active mode, the standby generator is weaker and slower, and consequently, is not very useful or effective.
An exemplary system used for reducing power consumption is described in U.S. Pat. No. 5,337,284 which is directed to a system implemented in an integrated circuit for generating high voltages for use in low-power applications. Particularly, U.S. Pat. No. 5,337,284 is directed to implementation of a voltage pump (charge pumps), comprising a standby pump and several active pumps. During a standby mode of operation, only a standby pump is left on in order to save power. A notable feature of U.S. Pat. No. 5,337,284 is the implementation of a self-timed clock circuit which obviates the requirement for a free-running oscillator.
Other state of the art on-chip power reduction systems includes U.S. Pat. Nos. 5,189,316, 5,856,951, and 5,315,557.
U.S. Pat. No. 5,189,316 is directed to a step-down voltage generator system comprising means for stepping-down an external supply voltage level (e.g., Vext) to an internal level (e.g., Vint) which is lower than the supply voltage level. In U.S. Pat. No. 5,189,316, during standby, the Vint generator is shut off and the Vint power buss is connected to the Vext to save power. A significant disadvantage of this approach is that the gate oxide at standby will be stressed more, possibly resulting in the need for thick-oxide devices for the circuits which will degrade the circuit performance. Another disadvantage is that, during standby, there will be also higher threshold and junction leakage due to the usage of the higher voltage supply.
U.S. Pat. No. 5,856,951 is directed to a system for generating a reduced Vint and elevated power source voltage Vss (typically at ground potential) to be used during a standby mode to cut down the standby power and leakage. This design requires extra hardware in order to create such extra supply levels. However, the extra area increase may not warrant the gain in the power saving. U.S. Pat. No. 5,315,557 describes a system for generating a refresh clock pulse in conjunction with a mechanism for disabling only a substrate bias generator, Vbb, during refresh operation to save power. The Vbb power generation circuit only consumes current in the microamp range which is not considered a significant power saving.
A reference authored by Ho-Jun Song entitled xe2x80x9cA Self-Off-Time Detector for Reducing Standby Current of DRAMxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 32, No. Oct. 10, 1997, pp 1535-1542, describes a timer circuit implemented for reducing standby current due to various voltage generators in DRAM circuits. In this reference, a built-in time detector circuit is provisioned for evaluating an xe2x80x9coff-timexe2x80x9d interval, i.e., the time elapsed for the monitored supply voltage at a first level to reach a predetermined second level in a first cycle of operation.
built in time detector then initiates sampling and re-pumping of the monitored supply voltage to the original first level at the end of the off-time interval and at each successive off-time interval for the duration of the standby period. This built-in time detector however, is a complex circuit and costly in terms of real estate, i.e., it takes up more chip area, and power consumption, as power itself is consumed during the first cycle time detection operation.
It would thus be highly desirable to provide an on-chip, self-refresh voltage generator system and method for reducing the power of all on-chip voltage generators during non-active mode periods while maintaining stable voltage levels on the semiconductor chip with minimum power consumption. As DRAM memory device designs have an ever increasing requirement to operate at reduced power levels, it would additionally be highly desirable to provide an on-chip, self-refresh voltage generator system operable for refreshing DRAM memory storage cells at reduced power consumption levels.
It is an object of the present invention to provide a system for controlling an internally supplied voltage level generated within an integrated circuit, and, for reducing the power of on-chip voltage generators during non-active mode periods while maintaining stable voltage levels on the semiconductor chip with minimum power consumption.
It is a further object of the present invention to provide an on-chip, self-refresh voltage generator system operable for refreshing DRAM memory storage cells at reduced power consumption levels.
It is another object of the present invention to provide an on-chip, self-refresh voltage generator system that leverages use of an existing on-chip self-refresh clock generator to perform a periodic wake-up task.
According to a first aspect of the invention, there is provided a system and method for controlling an internally supplied voltage level generated within an integrated circuit, the system comprising: a voltage supply generator providing a voltage source for internal, on-chip use and responsive to a low power enable signal for placing the system in a low power mode; and, a limiter device for intermittently sampling the internal voltage supply level during the low power mode, and for determining whether the internal voltage supply level falls below a predetermined voltage reference level, and, when the internal voltage supply level falls below the predetermined voltage reference level, the limiter device activating the voltage supply generator for increasing the internal voltage supply level, and deactivating the voltage supply generator when the voltage supply level is restored to said predetermined voltage reference level, whereby internally generated voltage levels are maintained throughout system low power operation.
Preferably the intermittent sampling cycle may be tailored according to internal chip condition, chip temperature, and chip size.
Advantageously, the on-chip, self-refresh voltage generator system of the invention may be implemented in any semiconductor chip, e.g., DRAM memory circuits, and obviates the need for a standby generator and related standby circuitry thus, reducing power consumption and chip real estate. Furthermore, the voltage control system may be implemented for every active voltage generator used for refresh operations and that is capable of being placed in a low power or xe2x80x9csleepxe2x80x9d mode for power conservation.
Further features, aspects and advantages of the apparatus and methods of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
FIG. 1 is a block diagram illustrating the on-chip, self-refresh voltage generator system 10 according to the principles of the invention.
FIG. 2 is a block diagram illustrating the DC voltage generator according to the principles of invention.
FIG. 3 illustrates the timing relationship of sleep_enable (SLEN) and sample_clock (SAMPLE) signals generated in accordance with the invention.
FIG. 4 is a flow chart depicting the operation of the sampling scheme implemented in accordance with the present invention.
FIG. 5 is a detailed schematic diagram illustrating an example sample clock generator circuit according to the principles of invention.
FIG. 6 is a detailed schematic diagram illustrating an example limiter circuit for the DC voltage generator according to the principles of invention.
FIGS. 7(a)-7(g) depicts the timing relation between various signals involved in the limiter control circuit provided in a DC generator circuit.
FIG. 8 is an example timing diagram illustrating the relationship between the differential amplifier input signals Vout, Vref and the differential amplifier output voltage signal operable for boosting voltage generator during the chip sleep mode.
FIG. 9 illustrates the on-chip, self-refresh voltage generator system 500 applied for reducing the power of multiple on-chip voltage generators.